楊宜霖 (Yi-Lin Yang)教授
個人學歷
國立台灣大學電子博士
研究專長
固態電子、半導體元件、記憶體元件
聯絡電話
(07)7172930 分機 7918
電子信箱
t3550@nknu.edu.tw
互動時段
週三：13：30 ~ 15：30
學經歷(Click)
學歷
經歷
| 畢業學校 | 主修學門系所 | 學位 | 起訖年月 |
| 國立台灣大學 | 電子工程研究所 | 碩博士 | 2002/09 至 2009/06 |
| 國立交通大學 | 電子工程系 | 學士 | 1998/09 至 2002/06 |
| 服務機關 | 服務部門／系所 | 職稱 | 起訖年月 |
| 美國耶魯大學 | 訪問學者 | 2008/05 至 2009/04 | |
| 國家奈米實驗室 | 研究助理 | 2010/01 至 2010/05 |
學術榮譽(Click)
| 年度 | 項目 |
| 2007 | 台積電傑出學生研究獎 佳作 |
期刊論文(Click)
| 項次 | 論文／期刊 |
| 1. | W. Zhang, T.-L. Wang, Y.-H. Huang, T.-T. Cheng, S.-Y. Chen, Y.-Y. Li, C.-H. Hsu, C.-J. Lai, W.-K. Yeh and Y.-L. Yang, “Influence of Fin Number on Hot-Carrier Injection Stress Induced Degradation in Bulk FinFETs,” Microelectronic Reliability, Vol. 67, No. 12, PP. 89-93, Dec. 2016 |
| 2. | W.-K. Yeh, W. Zhang, Y.-L. Yang, A.-N. Dai, K. Wu, T.-H. Chou, C.-L. Lin, K.-J. Gan, C.-H. Shih, and P.-Y. Chen, “The Observation of Width Quantization impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET,” IEEE Transactions on Device and Materials Reliability Vol. 16, No.12, PP. 610-616, Dec. 2016. |
| 3. | Y.-L. Yang, W. Zhang, T.-S. Yen, J.-J. Hong, J.-C. Wong, C.-C. Ku, T.-H. Wu, T.-L. Wang, C.-Y. Li, B.-T. Wu, S.-H. Lin and W.-K. Yeh, “Examination of Hot-Carrier Stress Induced Degradation on Fin Field-Effect Transistor,” Applied Physics Letters, Vol. 104, No. 2, PP. 083505, 2014 (SCI, IF=3.515) |
| 4. | Y.-L. Yang, W. Zhang, C.-Y. Cheng, Y.-P. Huang, P.-T. Chen, C.-W. Hsu, L.-K. Chin, C.-T. Lin, C.-H. Hsu, C.-M. Lai and W.-K. Yeh, “Reliability Improvement of 28nm High-k/Metal Gate-Last MOSFET using Appropriate Oxygen Annealing,” IEEE Electron Device Letters, Vol.33 , No.8, PP. 1183-1185, Aug. 2012 (SCI, IF=3.023) |
| 5. | Y.-L. Yang, W. Zhang, C.-Y. Cheng, W.-K. Yeh “The Improvement of Reliability of High-k/Metal Gate pMOSFET Device with Various PMA Conditions,” Active and Passive Electronic Components, Vol. 2012, Article ID 872494, doi:10.1155/2012/872494. (EI) |
| 6. | C.-N. Lin, Y.-L. Yang, W.-T. Chen, S.-C. Lin, K.-C. Chuang, and J.-G. Hwu, “Effect of Strain-Temperature Stress on MOS Structure with Ultra-thin Gate Oxide,” Microelectronics Engineering, Vol.85, PP.1915-1919., Sept. 2008 (SCI, IF=1.338) |
| 7. | Y.-L. Yang, C.-H. Chang, Y.-H. Shih, K.-Y. Hsieh, and J.-G. Hwu, “Modeling and Characterization of Hydrogen Induced Charge Loss in Nitride Trapping Memory,” IEEE Transactions on Electron Devices, Vol.54, No.6, PP.1360~1365, Jun. 2007 (SCI, IF=2.358) |
| 8. | C.-W. Tung, Y.-L. Yang and J.-G. Hwu, “Impact of Strain-Temperature Stress on Ultrathin Oxide,” IEEE Transactions on Electron Devices, Vol.53, No.7, PP.1736-1737, Jul. 2006 (SCI, IF=2.358) |
| 9. | Y.-L. Yang and J.-G. Hwu, “Quality Improvement of Ultra-Thin Gate Oxide by Using Thermal-Growth Followed by Scanning-Frequency Anodization (SF ANO) Technique,” IEEE Electron Device Letters, Vol.25, No.10, PP.687-689, Oct. 2004 (SCI, IF=3.023) |
| 10. | W.-J. Liao, Y.-L. Yang, S.-C. Chuang, and J.-G. Hwu, “Growth-Then-Anodization Technique for Reliable Ultra-Thin Gate Oxides,” Journal of The Electrochemical Society, Vol.151, No.9, PP.G549-G553, Sept. 2004 (SCI, IF=2.859). |
研討會論文(Click)
| 項次 | 論文 |
| 1. | W.-K. Yeh, P.-Y. Chen, W. Zhang, and Y.-L. Yang, “The Geometry Dependence on Device’s Performance and Reliability for Multi-Fin Tri-gate FinFETs,” IEEE Conference on Electron Devices and Solid-State Circuits, Hsinchu, Oct. 2017. |
| 2. | Y.-L. Yang, W. Zhang, C.-C. Hsu, Y.-L. Chen, C.-J. Lai, W.-H. Lo, W.-T. Huang, Y.-H. Lin, C.-H. Li and W.-K. Yeh, “Study on Hot Carrier Injection Induced FinFET Devices Degradation for Different Stress Conditions and Fin Numbers” International Electron Device and Material Symposium, Hsinchu, Sep., 2017. |
| 3. | W.-K. Yeh, P.-Y. Chen, C.-H. Shih, W. Zhang, and Y.-L. Yang, “The impact of fin number on device's performance and reliability in tri-gate FinFETs,” IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Feb. 2017. |
| 4. | A.-N. Dai, S.-Y. Chen, C.-K. Yang, Q.-F. Chung, W. Zhang, Y.-L. Yang and W.-K. Yeh, “Study the Reliability for Hot-Carrier Stress Induced Degradation on N-Channel FinFET Devices” International Electron Device and Material Symposium, Taipei, Nov., 2016. |
| 5. | S.-Y. Chen, C.-K. Yang, Q.-F. Zhuang, W. Zhang, Y.-L. Yang, W.-K. Yeh, “Impact of Metal-Gate on Device performance and Reliability of nFinFETs” International Electron Device and Material Symposium, Taipei, Nov., 2016. |
| 6. | W.-K. Yeh, W. Zhang and Y.-L. Yang, “Effects of Fin Width on Performance and Reliability for N- and P-type FinFETs” IEEE Conference on Electron Devices and Solid-State Circuits, Hong Kong, Aug. 2016. |
| 7. | T.-L. Wang, W. Zhang, Y.-H. Huang, W.-K. Yeh and Y.-L. Yang, “Study on Hot-Carrier Stress Induced Degradation on N-Channel FinFET Devices with Different Fin Numbers” International Symposium on Electrical, Electronic Engineering and Digital Technology, Tokyo, Dec. 2015 |
| 8. | S.-Y. Chen, T.-T. Cheng, Y.-Y. Chen, T.-L. Wang, Y.-L. Yang and W.-K. Yeh, “The Investigation of Characteristic and Reliability for Multi-Fin p-Channel FinFET” International Electron Device and Material Symposium, Tainan, Nov., 2015 |
| 9. | W.-K. Yeh, W. Zhang, Y.-L. Yang, “The Study on Width Quantization impact on Device Performance and Reliability for high-k/metal Tri-Gate FinFET” IEEE Conference on Electron Devices and Solid-State Circuits, Singapore, Jun. 2015. |
| 10. | J.-J. Hong, Y.-Y. Chen,T.-T. Cheng, T.-L. Wang, C.-Y. Li, W. Zhang, Y.-L. Yang and W.-K. Yeh, “Study on HCI and NBTI Induced Device Degradation for P-Channel FinFET”, International Electron Device and Material Symposium, Hualien, Nov., 2014 |
| 11. | Y.-L. Yang, J.-J. Hon, W. Zhang and W.-K. Yeh, “Study on Hot-Carrier Stress Induced Degradation on P-Channel FinFET Devices” Annual Conference on Engineering and Technology, Osaka, Oct. 2014. |
| 12. | N.-K. Mou, C.-H. Yeh, T.-S. Yen, Y.-Y. Chen, T.-T. Cheng, Y.-L. Yang and W.-K. Yeh, “Influence of Characteristic and Reliability on UTBB-SOI nMOSFETs” Symposium of Nano Device Technology, Hsinchu, May 2014. |
| 13. | J.-C. Wong, J.-J. Hong, Y.-Y. Chen, T.-T. Cheng, T.-S. Yen, Y.-L. Yang and W.-K. Yeh, “A Comparative Study of PBTI and Hot-Carrier Stress Induced Degradation on FinFET Devices” Symposium of Nano Device Technology, Hsinchu, May 2014. |
| 14. | J.-J. Hon, J.-C. Wong, Y.-Y. Chen,T.-T. Cheng, T.-S. Yen, Y.-L. Yang and W.-K. Yeh, “Study on Hot-Carrier Stress and Negative-Bias Stress Induced Degradation on P-Channel FinFET Devices” Symposium of Nano Device Technology, Hsinchu, May 2014. |
| 15. | Y.-L. Yang, C.-H. Yeh, Z.-S. Yan, W. Zhang, S.-H. Lin and W.-K. Yeh, “Investigation on HCI and PBTI for UTBB-SOI nMOSFETs with Various Dopant Concentrations” Annual Conference on Engineering & Information Technology, Tokyo Japan, Mar. 2014 |
| 16. | Y.-L. Yang, T.-S. Yen, J.-J. Hong, J.-C. Wong, C.-C. Ku, T.-H. Wu, T.-L. Wang, C.-Y. Li, B.-T. Wu, W. Zhang and W.-K. Yeh, “Study on Hot-Carrier Stress Induced Degradation on FinFET Devices” International Electron Device and Material Symposium, Nantou, Nov. 2013 |
| 17. | Y.-L. Yang, C.-M. Lai, W. Zhang, J.-J. Hung, J.-C. Weng, C.-H. Yeh, N.-K. Mou, S.-H. Wang, Z.-S. Yan, L.-K. Chin, S.-H. Lin and W.-K. Yeh, “Effects of Dose Conditions on PBTI in Ultra-Thin Body and Buried Oxide Silicon-on-Insulator (UTBB-SOI) nMOSFET”, IEEE Nanotechnology Materials and Devices Conference, Tainan, Oct. 2013. |
| 18. | W. Zhang, J.-H. Chang, Y.-H. Chen, Y.-L. Yang, C.-M. Lai, S.-H. Wang, L.-K. Chin and W.-K. Yeh, “Impact of Doping Concentration on Device Characteristic and Reliability in Ultra-Thin-Body and BOX (UTBB) MOSFETs”, International Electron Device and Material Symposium, Kaohsiung, Nov. 2012 (傑出論文獎) |
| 19. | W.-K. Yeh, W. Zhang, Y.-L. Yang and P.-Y. Chen, “A proposed high manufacturability strain technology for high-k/metal gate SiGe channel UTBB CMOSFET”, International Conference on Solid-State and Integrated Circuit Technology, Xi’an China, Oct. 2012 |
| 20. | Y.-L. Yang, W. Zhang, C.-Y. Cheng, Y.-P. Huang, P.-T. Chen, L.-K. Chin, C.-W. Hsu, and W.-K. Yeh, “Reliability Improvement of 28nm High-k/Metal Gate Device by Using Oxygen Annealing”, International Symposium on Integrated Functionalities, Hong kong, Jun. 2012 |
| 21. | Y.-L. Yang, Y.-P. Huang, P.-T. Chen, W.-Q. Zhang, C.-Y. Cheng, L.-K. Chin, C.-W. Hsu, and W.-K. Yeh, “Reliability Improvement of 28nm Gate Last High-k/Metal Gate Device with Oxygen Annealing,” International Electron Device and Material Symposium, Taipei, Nov. 2011 |
| 22. | W.-K. Yeh, C.-Y. Cheng, Y.-L Yang, C.-T. Lin, C.-M. Lai, Y.-W. Chen, C.-H. Hsu, C.-W. Yang, P.-Y. Chen, “A Proposed High Manufacturability Strain Technology for High-k/Metal Gate SiGe-SOI CMOSFET,” IEEE International SOI conference, Tempe Mission Palms Hotel and Conference Center, Tempe Arizona, USA, Oct. 2011. |
| 23. | C.-Y. Cheng, W.-K. Yeh, Y.-L. Yang, and C.-W. Hsu, “The Improvement of Reliability of 28nm High-k/Metal Gate Device with Various PMA Conditions” Symposium of Nano Device Technology, Hsinchu, Apr. 2011 |
| 24. | Z. Liu, X.-W. (Sharon) Wang, W. Zhang, Y.-L. Yang and T.-P. Ma, “Inelastic Electron Tunneling Spectroscopy Study of Ultra-Thin TiO2/Al2O3 on GaAs,” IEEE Semiconductor Interface Specialists Conference, Key Bridge Marriott Hotel, Arlington VA, USA, Dec. 2009 |
| 25. | J.-F Yang, X.-W. (Sharon) Wang, Y.-L. Yang and T.-P. Ma, “Charge Trapping Memory Stack with Aluminum Oxide as the Tunnel Barrier,” IEEE Semiconductor Interface Specialists Conference, Catamaran Resort Hotel, San Diego CA, USA, Dec. 2008 |
| 26. | (Invited) C.-N. Lin, Y.-L. Yang, W.-T. Chen, S.-C. Lin, and J.-G. Hwu, “Investigation of Strain-Temperature Stress Effects on the Characteristics of MOS Capacitors with Ultra-thin Gate Oxides,” IEEE International Conference on Electron Devices and Solid-State Circuits, Tayih Landies Hotel, Tainan, Taiwan, Republic of China., Dec. 2007 |
| 27. | Y.-L. Yang, C.-H. Chang, Y.-H. Shih, K.-Y. Hsieh, and J.-G. Hwu, “Hydrogen Eraser for Tightening VT Distribution of Nitride Trapping Memory,” Proceedings of International Electronic Devices and Materials Symposium, Vol. A & D, PP.303-304, National Cheng-Kung University, Tainan, Taiwan, Republic of Chin, Dec. 2006 |
研究計畫(Click)
| 計畫名稱 | 擔任工作 | 執行時間 | 補助單位 |
| 具不同摻雜濃度之超薄絕緣層上矽晶及超薄底絕緣層金氧半場效電晶體閘極絕緣層可靠度之分析與探討 | 主持人 | 2015/08/01~2016/07/31 | 科技部 |
| 非平面結構金氧半場效電晶體閘極絕緣層可靠度之分析與探討 | 主持人 | 2014/08/01~2015/07/31 | 科技部 |
| 電阻式記憶體之低能耗製程技術開發(Ⅱ) | 主持人 | 2013/08/01~2014/07/31 | 國科會 |
| 電阻式記憶體之低能耗製程技術開發(Ⅰ) | 主持人 | 2011/08/01~2012/07/31 | 國科會 |
專利著作(Click)
| 專利名稱 | 專利號碼 | 發明人 | 專利日期 |
| METHOD FOR FABRICATING CHARGE-TRAPPING MEMORY | US Patent No. 7778072. | Y.H. Shih, A. Hsieh, Y.L. Yang, C.H. Chang, and J.G. Hwu |
